This invention relates, in general, to three dimensional integrated circuits. More particularly, the present invention relates to a specific configuration for three dimensional integrated circuits and a method of constructing same. In order to increase circuit density, semiconductor manufacturers have continued to reduce the size of various integrated circuit elements and interconnections to the point where the limits of current technology are being reached. In order to decrease run length and increase circuit density, various methods have been explored to interconnect a plurality of integrated circuit chips without the use of a circuit board. Some of the methods proposed to date include wafer scale integration, stacking individual devices horizontally and stacking individual devices vertically.
It would, therefore, be advantageous to combine a number of integrated circuits in a three dimensional interconnected module such that for a given device footprint the total integrated circuit surface area would increase by a factor of 2, 3, 4 or more. This increased circuit area could be used to either add additional functions to a given circuit or provide redundancy in areas where desired. It would be desirable to accomplish this increase in integrated circuit area while at least retaining, if not improving, the heat dissipation capability of the original circuit. In addition, a method should be provided wherein the individual circuit elements may be easily interconnected among themselves and to any external circuits. Such an arrangement would also decrease the run length between the individual circuit chips thereby reducing both the power required for transmitting signals between the individual chips and the time required for such signals to be transmitted between such chips. In those devices where run lengths are not critical, expanding the formats of existing devices would restore greater line widths and therefore result in greater yields.